MSc David Spielmann
david.spielmann@unisg.ch
david-spielmann-74a10919a
0009-0004-1715-2059
DaSpielmann
davidspielmann

School of Computer Science
Torstrasse 25
9000 St. Gallen, Switzerland

I joined the Programming Group as a PhD student in May 2023. I obtained my Bachelor’s degree in Computer Science from ETH Zurich and a joint Master’s degree from ETH Zurich and EPF Lausanne with a focus on security and distributed systems. As part of my Master’s thesis, I used to examine power side-channel attacks on remotely accessible FPGAs. In my PhD studies, I focus on my research interests which include software engineering and security.

Publications

1. TSE
   ProTI
   

   Automated Infrastructure as Code Program Testing

   Daniel Sokolowski, David Spielmann, Guido Salvaneschi

   IEEE Transactions on Software Engineering, 2024

   PDF Supp Code Website
2. ICSE Companion
   ProTI
   

   Unleashing the Giants: Enabling Advanced Testing for Infrastructure as Code

   Daniel Sokolowski, David Spielmann, Guido Salvaneschi

   In Companion Proceedings of the 46th International Conference on Software Engineering, ICSE Companion, 2024

   PDF
3. MSR
   

   The PIPr Dataset of Public Infrastructure as Code Programs

   Daniel Sokolowski, David Spielmann, Guido Salvaneschi

   In Proceedings of the IEEE/ACM 21st International Conference on Mining Software Repositories, MSR, 2024

   PDF
4. TCHES
   

   RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

   David Spielmann, Ognjen Glamočanin, Mirjana Stojilović

   IACR Transactions on Cryptographic Hardware and Embedded Systems 198 (2), 2023

   Abstract PDF

   State-of-the-art sensors for measuring FPGA voltage fluctuations are time-to-digital converters (TDCs). They allow detecting voltage fluctuations in the order of a few nanoseconds. The key building component of a TDC is a delay line, typically implemented as a chain of fast carry propagation multiplexers. In FPGAs, the fast carry chains are constrained to dedicated logic and routing, and need to be routed strictly vertically. In this work, we present an alternative approach to designing on-chip voltage sensors, in which the FPGA routing resources replace the carry logic. We present three variants of what we name a routing delay sensor (RDS): one vertically constrained, one horizontally constrained, and one free of any constraints. We perform a thorough experimental evaluation on both the Sakura-X side-channel evaluation board and the Alveo U200 datacenter card, to evaluate the performance of RDS sensors in the context of a remote power side-channel analysis attack. The results show that our best RDS implementation in most cases outperforms the TDC. On average, for breaking the full 128-bit key of an AES-128 cryptographic core, an adversary requires 35% fewer side-channel traces when using the RDS than when using the TDC. Besides making the attack more effective, given the absence of the placement and routing constraint, the RDS sensor is also easier to deploy.

5. CONFLANG
   ProTI
   

   Creed for Speed: Comprehensive Infrastructure as Code Testing

   Daniel Sokolowski, David Spielmann, Guido Salvaneschi

   Presentation at the CONFLANG 2023 workshop, 2023

   Abstract PDF

   With Programming Languages Infrastructure as Code (PL-IaC), developers implement imperative IaC programs in one of many general-purpose programming languages, e.g., TypeScript, Python, or Go, to declaratively describe deployments. Using these languages provides access to quality assurance techniques and tools developed for traditional software; however, programmers routinely rely on prohibitively slow integration testing – if they test at all. As a result, even simple bugs are found late, tremendously slowing down the development process.

   To improve the velocity of PL-IaC development, we propose ProTI, an automated unit testing approach that quickly tests PL-IaC programs in many different configurations. ProTI mocks all cloud resources, replacing them with pluggable oracles that validate all resources configurations and a generator for realistic test inputs. We implemented ProTI for Pulumi TypeScript with simple generator and oracle plugins. Our experience of testing with ProTI encourages the exploration of more sophisticated oracles and generators, leading to the early detection of more bugs. ProTI enables programmers to rapidly prototype, explore, and plug in new oracles and generators for efficient PL-IaC program testing.

6. SPLASH Companion
   ProTI
   

   Extensible Testing for Infrastructure as Code

   David Spielmann, Daniel Sokolowski, Guido Salvaneschi

   In Companion Proceedings of the 2023 ACM SIGPLAN International Conference on Systems, Programming, Languages, and Applications: Software for Humanity, SPLASH Companion, 2023

   Abstract PDF

   Developers automate deployments with Programming Languages Infrastructure as Code (PL-IaC) by implementing IaC programs in popular languages like TypeScript and Python. Yet, systematic testing—well established for high-velocity software development—is rarely applied to IaC programs because IaC testing techniques are either slow or require extensive development effort. To solve this dilemma, we develop ProTI, a novel IaC unit testing approach, and implement it for Pulumi TypeScript. Our preliminary experiments with simple type-based test case generators and oracles show that ProTI can find bugs reliably in a short time, often without writing any additional testing code. ProTI’s extensible plugin architecture allows combining, adopting, and experimenting with new approaches, opening the discussion about novel generators and oracles for efficient IaC testing.